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• Msee: Full-Time at Gould and Motorola While Taking Classes, Part-Time While Finishing Thesis.Invented Harrm, the Hardware Register Renaming Mechanism, Which Became the P6 Rat (And Which is Now the Renaming Technique Used by Most Modern Microprocessors - it was Supposed to be One of the &Quot;Big Innovations&Quot; in the Alpha Ev8/21464). {I Wish That i had Patented It.}Refined Ideas for Out-Of-Order Cpu Microarchitecture That Evolved Into the Intel P6.Ms Thesis was on &Quot;A Feature… Show More Msee: Full-Time at Gould and Motorola While Taking Classes, Part-Time While Finishing Thesis.Invented Harrm, the Hardware Register Renaming Mechanism, Which Became the P6 Rat (And Which is Now the Renaming Technique Used by Most Modern Microprocessors - it was Supposed to be One of the &Quot;Big Innovations&Quot; in the Alpha Ev8/21464). {I Wish That i had Patented It.}Refined Ideas for Out-Of-Order Cpu Microarchitecture That Evolved Into the Intel P6.Ms Thesis was on &Quot;A Feature Taxonomy of Synchronization Primitives, Including the Bus Abandonment Lock&Quot;. I.E. Multiprocessor Synchronization, Locking, and Cache Protocols.Pointed Out Livelock Problems with Risc Ll/Sc (Load Linked / Store Conditional), That i was Involved in Mitigating Circa 20-30 Years Later at Mips. Show Less
• Activities and Societies: Hoofers Outing Club Pursued Ph.D. Cs, Computer Architecture, Under Prof. Guri Sohi. Intel Scholar. Returned to Intel When: (A) Daughter Born, (B) Promised New Project.Never Got MY Ph.D. :-(, Although i did Make Several Significant Advances in Computer Architecture :-), Including:(1) Hardware Performing Compiler Like Optimizations on the Fly, Such as Dynamic Instruction Rewriting and Instruction Refinement: Flattening / Dynamic Path Length Reduction / Hardware Parallel Prefix, and Dynamic Common… Show More Pursued Ph.D. Cs, Computer Architecture, Under Prof. Guri Sohi. Intel Scholar. Returned to Intel When: (A) Daughter Born, (B) Promised New Project.Never Got MY Ph.D. :-(, Although i did Make Several Significant Advances in Computer Architecture :-), Including:(1) Hardware Performing Compiler Like Optimizations on the Fly, Such as Dynamic Instruction Rewriting and Instruction Refinement: Flattening / Dynamic Path Length Reduction / Hardware Parallel Prefix, and Dynamic Common Sub-Expression Elimination.(2) Developed Mlp, Memory Level Parallelism, Concept, Including Hardware Skip Pointers for Linked Data Structures Using Space Freed UP in Cache Lines by Compression.(3) Developed Speculative Multithreading Microarchitectures (Imt/Dmt/Spmt/Skmt), Including Multicluster Multithreaded (Mcmt), Multilevel Schedulers, Trace Log Execution.(4) Multilevel Branch Predictorsalso: Perlsql, Agile/Xp. Show Less
• Activities and Societies: Engineering Flag Football, Broomball, and Soccer: the Generators! Class Project: Seism, Small Efficient Instruction Set Machine: MY Own Take on Risc, Motivated by Ooo. Tools to Automatically Generate Instruction Set, Manuals, and Tools Such as Decoders and Disassemblers.